Published on Apr 02, 2024
In this fast moving world time delay is one of the most dreaded situations in the field of data communication. A delay in the communication is as bad as loosing the information, whether it is on the internet or on television or talking over a telephone. We need to find out different ways to improve the communication speed. The various methods adopted by the communication industry are the wireless technology, optical communications, ultra wide band communication networks etc.
But all these methods need an initial capital amount which makes all these methods cost ineffective. So improving the existing network is very important especially in a country like INDIA.
The communication systems mainly consist of a transeiver and a channel. The tranceiver is the core of all data communications. It has a very vast variety of electronic components mostly integrated into different forms of IC chips. These ICs provide the various signal modifications like amplification, modulation etc. The delay caused in these circuits will definitely affect the speed of data communication.
This is where this topic LOW-k DIELCTRICS becomes relevant. It is one of the most recent developments in the field of integrated electronics. Mostly the IC s are manufactured using the CMOS technology. This technology has an embedded coupling capacitance that reduces the speed of operation. There are many other logics available like the RTL,DTL,ECL,TTL etc . But all these other logics have higher power consumption than the CMOS technology. So the industry prefer CMOS over other logics .
Inside the IC there are lots of interconnections between points in the CMOS substrate. These refer to the connection between the different transistors in the IC. For example , in the case of NAND LOGICS there are lots of connections between the transistors and their feedbacks. These connections are made by the INTERCONNECT inside the IC . Aluminum has been the material of choice for the circuit lines used to connect transistors and other chip components. These thin aluminum lines must be isolated from each other with an insulating material, usually silicon dioxide (SiO2).
This basic circuit construction technique has worked well through the many generations of computer chip advances predicted by Moore's Law1. However, as aluminum circuit lines approach 0.18 mm in width, the limiting factor in computer processor speed shifts from the transistors' gate delay to interconnect delay caused by the aluminum lines and the SiO2 insulation material. With the introduction of copper lines, part of the "speed limit" has been removed. However, the properties of the dielectric material between the layers and lines must now be addressed. Although integration of low-k will occur at the 0.13mm technology node, industry opinion is that the 0.10mm generation, set for commercialization in 2003 or 2004, will be the true proving ground for low-k dielectrics because the whole industry will need to use low-k at that line width.
Any process change in the semiconductor industry is difficult, but choosing a new dielectric material has been (and continues to be) an exercise in trying to find a low-k dielectric film with electrical, thermal and mechanical properties comparable to or better than those of SiO2 (e.g., good hardness, adhesion, etc).
At this time, there is no standard for these new materials and no material has yet to gain an advantage. Significant differences in applications and chip architecture may preclude such a standard. However, Ting8 and others were able to generate a generic list of the most critical dielectric requirements. This list is shown in Table 1.
Although Table 1 contains many properties, several of the more important properties of a dielectric include the following:
• Good thermal stability and low coefficient of thermal expansion. These properties are needed to prevent both damage to the film or property changes during subsequent thermal processes.
• An isotropic dielectric constant of less than 3.0. Also, when combined with barrier layers, the effective dielectric “stack” should have an effective k of less than 3.0. Typically, a barrier dielectric material is needed below and above the main dielectric material. This creates a dielectric stack, largely determining the line-to-line capacitive coupling and RC interconnect delay. It does no good to combine the low-k dielectric with highly capacitive barrier layers since having a low effective k is the very reasons for adopting a low-k material in the first place.
• Good adhesion. Adhesion is particularly key, especially for organic spin-on materials that often do not adhere well to standard CVD oxide and nitride films, or barrier metals including Ti, TiN, Ta and TaN. This is a serious issue as the chemical mechanical planarization (CMP) process can cause deformation or removal of dielectric layer during damascene or dual damascene processing.
• Etch and Strip resistance. The potential for via poisoning comes from etching and resist removal. Etch processes have to be optimized for profile control and, importantly, zero damage. The stripping process replaces the traditional oxidizing chemistry with a hydrogen-based reducing chemistry.
• Commercial availability and low cost of ownership.
Finding polymers with low dielectric constants is a relatively easy task. However, finding those with the required chemical, mechanical, electrical and thermal properties for use in integrated circuit applications is more difficult. Much effort has gone into these searches and Table 2 provides a list of industry recognized dielectric material candidates for the 0.13m and 0.1m technology nodes.
Although all of these may be suitable for the 0.13m technology node, not all are suitable for the 0.1m node. For some materials, the k value is not low enough, while for others there are properties of the material that eliminate it as an option. The following sections discuss the advantages and disadvantages of each type of spin-on material.
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